OpenSBI

CHERI-enabled fork of OpenSBI: An open-source reference implementation of the RISC-V SBI specifications for platform-specific firmwares executing in M-mode.

Project Home: https://github.com/CHERI-Alliance/opensbi

Downloads & Documentation

Fork VersionBased on Upstream VersionTargetDownload
669eba1 (codasip-cheri-riscv)
2025-11-14		1.5
2024-08-02		riscv64cSource
There are no pre-built binaries or versioned releases.

Project Status

Active development takes place in the CHERI-Alliance/opensbi repository on the codasip-cheri-riscv branch.

Building from Source

Please keep an eye out for our blog as we will soon share instructions for building from source.

Get Involved

Development for this project happens in the following places:

The active repository is CHERI-Alliance/opensbi on the codasip-cheri-riscv branch which supports RISC-V RVY.

Earlier work can be found in CTSRD-CHERI/opensbi which is based on an old version of OpenSBI (0.8). However, this isn’t maintained or used and lacks support for the open RVY extension.

There are no mailing lists associated with this project.

There are no dedicated Slack channels, however support may be available in the CHERI CPU Slack in the #general channel.

There are no regular meetings associated with this project.

Vulnerability Disclosure

Please report security vulnerabilities relating to OpenSBI to support@thecapablehub.org.

Something missing, incorrect?

This page was last updated on 29th January 2026. Please let us know of any corrections via support@thecapablehub.org, alternatively raise a GitHub pull request in our repo.